High performance system on chips (SoCs), such as security devices, multi-purpose integrated circuit (IC) card chip and subscriber identification module (SIM), may utilize a non-volatile memory device which may include larger memory density, higher access speed and/or higher reliability. Ferroelectric random access memory (FRAM) devices may satisfy those requirements because the FRAM devices may have advantages of higher access speeds and/or lower power consumption. However, the conventional FRAM devices may not be fabricated such that they may be used in the SoCs.
A ferroelectric memory device which may use a (111) metal organic chemical vapor deposition Pb(Zr,Ti)O3 (MOCVD PZT) as a ferroelectric layer of a capacitor, a recessed iridium (Ir) barrier, and a higher temperature mask etching process may increase the switching charge and/or improve the reliability.
As illustrated in FIG. 1, a ferroelectric capacitor 70 may be formed on a tungsten plug 10. A recessed Ir barrier 20 may be formed to oxidize the tungsten plug 10 and to reduce the height of the capacitor 70. A lower electrode 40 may be formed of iridium (Ir) and MOCVD PZT may be deposited at a higher temperature (for example, 620° C.) to form a (111) oriented ferroelectric layer 50. Iridium oxide (IrOx) may be deposited to form an upper electrode 60, and a higher temperature mask etching process may be performed at a temperature of 400° C. to form the capacitor 70 which may have a higher aspect ratio. An encapsulation layer 30 may be formed and may cover the entire capacitor 70.
The upper electrode 60 may maintain a larger area thereof due to a recessed iridium barrier 20 after the higher temperature mask etching process and the angle of a flank of capacitor 70 may be approximately 70°.
FIG. 1A is a cross-sectional view of the ferroelectric memory device and FIG. 1B is an SEM photograph of a ferroelectric capacitor.
FIG. 2 illustrates X-ray diffraction patterns of MOCVD PZTs formed in a 620° C. process and in a conventional 580° C. process, respectively. As illustrated in FIG. 2, the PZT (marked with a solid line) may be deposited at a temperature of 620° C. using a seeding layer and may have a (111) oriented crystal growth, however the PZT (marked with a dotted line) which may be deposited at a temperature of 580° C. without the seeding layer may have a randomly oriented crystal growth.
Referring to FIG. 3, the PZT grown at 580° C. may have a randomly oriented granular structure, but the PZT grown at 620° C. may have a (111) orientated columnar structure. The PZT with the columnar structure may have improved crystal quality.
In a retention test, as illustrated in FIG. 4, the switching charge on the (111) oriented PZT capacitor (closed circles) may be stable with aging time, and the switching charge on the randomly oriented PZT capacitor (open squares) may decrease. More specifically, as illustrated in FIG. 5, the switching charge on the (111) oriented PZT capacitor (closed circles) may be stable, while the switching charge on the randomly oriented PZT capacitor (open squares) may decrease (for example, to nearly zero).
A recessed Ir barrier may be formed on a tungsten plug and iridium (Ir) may be deposited on the lower electrode. Fabrication of the recessed Ir barrier may be complex because it may utilize an Ir deposition, etching, and/or chemical mechanical polishing (CMP) processes.
As the capacitor area may decrease, which may be a result of an increase of a device integration density, the probability of causing misalignment may increase during photolithographic processes which may be used to form the recessed Ir barrier and the lower electrode.
The (111) oriented PZT may utilize a higher temperature (for example, 620° C.) to be deposited, and therefore the process temperature of the MOCVD may be increased to deposit the PZT, such that structural and/or operational problems may arise due to the higher temperature.